`timescale 1ns / 1ps
// (C) 2022 Intel Corporation. All rights reserved.
// Your use of Intel Corporation's design tools, logic functions and other 
// software and tools, and its AMPP partner logic functions, and any output 
// files from any of the foregoing (including device programming or simulation 
// files), and any associated documentation or information are expressly subject 
// to the terms and conditions of the Intel Program License Subscription 
// Agreement, Intel FPGA IP License Agreement, or other applicable 
// license agreement, including, without limitation, that your use is for the 
// sole purpose of programming logic devices manufactured by Intel and sold by 
// Intel or its authorized distributors.  Please refer to the applicable 
// agreement for further details.

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
module InputsSyncWithDefault #(
	parameter SIZE = 1,
	parameter DEFAULT_OUT = 1
)(
    //% Clock
    input               i_Clk,
    //% Reset
    input               i_Rst_n,
    //% Inputs Vector to be synchronized
    input   [SIZE-1:0]  i_vSync,
    //% Synchronized vector
    output  [SIZE-1:0]  o_vSync
);

//////////////////////////////////////////////////////////////////////////////////
// Instances
//////////////////////////////////////////////////////////////////////////////////
genvar i;
generate
    for (i=0; i<SIZE; i=i+1)
    begin: SyncBlock
    SyncWithDefault #(
	 .DEFAULT_OUT(DEFAULT_OUT)
	 )	mISyncWithDefault
    (
        .i_Clk           (i_Clk), 
        .i_Rst_n         (i_Rst_n), 
        .i_Signal        (i_vSync[i]), 
        .o_SyncSignal    (o_vSync[i])
    );
    
    end
endgenerate

//////////////////////////////////////////////////////////////////////////////////
endmodule
